1. Field of the Invention
The present invention relates to a voltage controlled oscillator capable of changing an oscillation frequency with a control voltage.
Priority is claimed on Japanese Patent Application No. 2007-39025, filed Feb. 20, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
A voltage controlled oscillator (VCO) has generally been used as a circuit for generating digital waveforms.
In particular, a VCO with the structure shown in FIG. 9 that uses differential delay elements shown in FIGS. 8A and 8B has been widely employed as a phase locked loop (PLL) for internal clock generation in a synchronous LSI (for example, refer to William J. Dally and John W. Poulton, “Digital Systems Engineering Basic Edition”, trans. Tadahiro Kuroda, Maruzen, Mar. 30, 2003, p. 747).
In the above-mentioned differential delay element, an N-channel type MOS transistor N100 into which a bias voltage signal NBIAS is inputted is used as a constant current source that provides a constant current I. Moreover, this differential delay element consists of P-channel type MOS transistors P100 and P101 into which a bias signal PBIAS is input, and diode-connected P-channel type MOS transistors P102 and P103 that are connected in parallel to the MOS transistors P100 and P101, respectively. This parallel circuit forms resistance of resistance value R.
The VCO shown in FIG. 9 operates with the gap between the differential nodes (the point of turnback at the maximum value and minimum value of the oscillating wave) being amplitude RI(=VDD−Vlow, with VDD being the power supply voltage, which is the maximum voltage in the output waveform, and Vlow being the minimum voltage in the output waveform).
By adjusting the abovementioned bias voltage signals NBIAS and PBIAS and mainly controlling the current value I, the propagation period (namely, delay time) of the differential delay element is changed, and so the oscillating frequency of the VCO is changed.
The signals CT1 to CT8 and CB1 to CB8 that are output from each of the differential delay elements 101 to 108 propagate while being delayed in turn by the differential delay elements of the next stage as in the waveform shown in FIG. 10. Thereby, it is possible to generate a multi-phase clock signal in which the signal CT4 has a phase difference of 90 degrees, the signal CB8 has a phase difference of 180 degrees, and the signal CB4 has a phase difference of 280 degrees with respect to the signal CT8 in a locked state of the frequency being stabilized.
Moreover, the phase difference of the outputs between the adjacent differential delay elements is 22.5 degrees (360 degrees/16). By interpolating this phase difference, it is possible to readily generate a multiphase clock that is synchronized with a signal that differs from the reference clock of the PLL.
However, the VCO mentioned above may fall into a the false oscillation state in which the phase differences between the differential delay elements shift from the design values due to the reason given below.
That is, since each of the differential delay elements (101 to 108 of FIG. 9) shown in FIGS. 8A and 8B has a small phase difference with another adjacent differential delay element, feedback is not applied to the voltage of the output terminals OUTP and OUTM other than weak feedback.
For that reason, as shown in FIG. 11, in the differential delay elements (101 to 108) that form the VCO by being connected in series, a metastable condition exists in which the signal waveforms of CTi, CBi that are even numbered (i=2, 4, 6, 8) are all in the same phase, while the signal waveforms of the odd-numbered CTj, CBj (j=1, 3, 5, 7) are in a reverse phase of the signal waveforms of the even-numbered CTi, CBi (first problem).
The phenomenon above easily occurs in the case of lowering the bias voltage signal in order to perform control that lowers the operating frequency of the VCO and dropping the gain of the differential delay elements. In this false oscillation state, the VCO cannot generate and output the intended multiphase clock as a designed value. That is, the phases of adjacent differential delay elements shift by 180 degrees each, leading to a state of the normal phase difference of 22.5 degrees between adjacent differential delay elements not being satisfied.
Moreover, the VCO may enter the metastable oscillation state as shown in FIG. 12. This false oscillation state is a stable state in which CTi (i is even number) and CBi all become the “L” level low-voltage level Vlow, and CTj (j is odd number) and CBj all become the “H” level high-voltage level VDD (second problem).
Also in this case, it is not possible to generate the intended multiphase clock as in the case of FIG. 11 and not possible to readily escape from the metastable state, and so returning to the normal oscillation state is difficult.